1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more specifically to a method of forming an alignment mark during the fabrication of semiconductor devices.
2. Description of Related Art
In semiconductor integrated circuit (IC) fabrication processes, multiple layers of conductors and insulators are patterned and built one upon the other to construct the IC. During the fabrication process it is critical to align each subsequent layer to a previous layer with great precision in order to preserve circuit continuity. The degree of alignment precision is often a major factor which determines the manufacturability, yield, and profit of a process.
The alignment of one layer to the next is typically accomplished in a tool called a wafer stepper. The purpose of the stepper is to transfer a desired pattern situated on a reticle into a layer formed on the semiconductor wafer. (The reticle typically contains a magnified (5.times.) version of the pattern to be generated.) As is well known in the art, in a typical alignment operation, a semiconductor wafer, having an alignment mark, is coated with a transparent photosensitive material (generally referred to as photoresist). The wafer is then loaded into the wafer stepper tool. The stepper uses the alignment mark on the wafer as a reference point in adjusting the position of the reticle over the wafer to precisely align the reticle to the previous layer on the wafer.
Generally, a stepper utilizes a laser beam with a fixed wavelength to sense the position of the alignment mark on the wafer. The laser beam in the stepper is bounced off of the alignment mark on the semiconductor wafer surface to create a slonal pattern of laser light. The defraction from the alignment mark is reflected back to sensing devices in the stepper and is used as a signal to measure the exact position of the alignment mark. The quality of the defractive light from the alignment mark is a direct result of the structure of the alignment mark (i.e., a result of the materials and dimensions of the mark).
General problems associated with present techniques of generating alignment marks and aligning wafers are illustrated in FIGS. 1a-1g. As shown in FIG. 1a, individual integrated circuits 122 are generated in each stepping field of the stepper. Generally there are two blank stepping fields 120 which are skipped during alignment and exposure of the various reticles used to pattern the wafer. A very small rectangular alignment mark 102 is typically formed near the center of each blank stepping field 120. Alignment mark 102 is very small in relationship to blank stepping field 120.
An alignment mark 102 is generally formed by etching a control distance into the semiconductor wafer 100, as shown in FIG. 1b. The etching step forms a step height 104 in the wafer 100. The step height 104 acts as the alignment mark. Step height 104 of alignment mark 102 is generally chosen to be some multiple, typically 1/4, of the wavelength of the laser light used by the stepper to conduct alignment. By utilizing an alignment mark which is a 1/4 multiple of the laser wavelength, the signal to noise ratio of the laser defraction is optimized, resulting in optimum alignment precision.
Next, as shown as FIG. 1c, subsequent layers used to form the integrated circuit are grown and deposited over the wafer. For example, field isolation regions 106, polysilicon conductors 108, and interlayer dielectrics (ILDs) 110 are grown and deposited respectively over the semiconductor wafer. Although the original alignment mark 102 is covered by subsequent layers, the step height 104 and the therefore, the alignment mark 102, is replicated in the subsequently deposited layers. The replicated alignment marks are used for aligning and patterning the subsequent layers. That is, as more layers are added to the IC, the step height of the alignment mark is propagated upward or is "built upward" with subsequent layers. The step height of the alignment mark is therefore preserved in subsequent layers so that alignment of subsequent layer can be accomplished.
A problem with building up the alignment mark is that it is incompatible with global planarization techniques, such as chemical-mechanical polishing. As more and more layers are added to the IC process, and circuit density increases, the requirement to planarize the IC topography at intermediate steps in the process becomes essential. It is important to planarize surfaces of multilevel integrated circuits because nonplanar surfaces interfere with the optical resolution of subsequent photolithography processing steps. This makes it extremely difficult to print high resolution lines. Additionally, nonplanar surface topographies can effect subsequently formed metal layers. If a step height is too large, there is a serious danger that open circuits will be formed in later metal layers. It has been found that the best way to planarize the IC topography is to planarize the ILDs and to use a global planarization technique, such as chemical-mechanical polishing. Global planarization techniques planarize the entire wafer surface and make the surface essentially fiat. Unfortunately, if ILD 110 is globally planarized, not only is the ILD 110 over the IC area 100 planarized, but so is the ILD 110 over the alignment mark. The global planarization technique, therefore, removes the alignment mark replicated in ILD 104, as shown in FIG. 1d.
Although the alignment mark has been removed during the global planarization step, the next process step, which is typically a contact etch step, can still proceed because the alignment mark 104 is visible through transparent ILD 110. That is, the contact etch pattern step can be aligned to the step height formed in polysilicon layer 108.
The next step in the fabrication of ICs typically is the formation of metal interconnects. As shown in FIG. 1e , a metal layer 112 is blanket deposited over ILD 110 and into contact 117, so that an electrical connection can be made with the polysilicon layer 108. Because metal layers are opaque, the step height 104 of alignment mark 102 formed in polysilicon layer 108 is invisible to the stepper laser. Without a visible alignment mark or an alignment mark replicated in metal layer 112, it is impossible to align the reticle to generate the metal interconnection pattern.
One solution to the planarized alignment mark problem is an "open frame" process. In an open frame process, after contact alignment, a separate reticle (an open frame reticle) is used to expose the area immediately surrounding alignment mark 102. ILD 110 over alignment mark 102 can then be etched away during the contact etch. Metal layer 112 can then be formed over uncovered alignment mark 102 formed in polysilicon layer 108, as shown in FIG. 1f. Alignment mark 102 replicated in metal layer 112 can then be used to align the reticle to generate of the metal interconnect pattern.
The "open frame" solution works fine in processes that require only one global planarization step. Many IC processes, however, require two global planarization steps. When a second global planarization step is required, it is not feasible to repeat the open frame alignment etch, due to the increased thickness of the dielectric material over the alignment mark. That is after the second global planarization, the depth of the dielectric material over the alignment mark is increased by the depth of the original open frame etch in comparison to the relevant structures on the IC. As a result, if one were to use a second open frame etch, chances are the relevant structure on the IC could not withstand the additional etching required to open the alignment mark.
Another solution to the planarized alignment mark problem, as shown in FIG. 1g, is to form a second completely independent alignment mark in ILD 110. In this process, after global planarization and contact formation, an exclusive masking and etching step is used to form a new alignment mark in ILD 110. This process requires considerable additional processing which adds no new value to the fabricated IC. This technique, therefore, is cost prohibitive.
Thus, what is required is a method of fabricating an alignment mark during multilayer semiconductor processes which is compatible with global planarization techniques, such as chemical-mechanical polishing (CMP) and which does not add additional cost or complexity to the fabrication process.